Alchitry Pt V2 Artix-7 FPGA Development Board

This is a platinum-tier FPGA development board designed for high-speed performance in compact builds. Its low-profile backside has no components taller than 1.5mm, enabling the use of high-speed 1.5mm stack-height DF40 connectors for GTP-capable interfaces such as PCIe 2.0.

At the centre is a Xilinx Artix-7 FPGA with a large resource set for ambitious digital logic projects, including real-time signal processing and high-speed communication. The board brings out extensive IO, dedicated DSP resources, Block RAM, DDR3L memory, configuration flash and USB-based JTAG/UART/FIFO connectivity.

As part of the modular Alchitry ecosystem, the Pt V2 stacks with expansion boards called Elements to add prototyping spaces, buttons, LEDs and more. To make a proper physical connection with its high-speed connectors, it requires a Br, Fn or Sp Element when connecting to an Ft, Ft+ or Hd board, preventing the connectors from contacting capacitors on the bottom of the Pt.

The Artix 7 FPGA requires a free Vivado licence. Supporting documentation includes the schematic, 3D Model (STEP), DC and AC Switching Characteristics (DS181), SelectIO Resources (UG471), Clocking Resources (UG472) and Xilinx Artix 7 documentation.

Features:

• Flagship FPGA platform: Platinum-tier FPGA development board engineered for high-speed performance and compact designs.
• Low-profile stacking: Backside features no components taller than 1.5mm for high-speed 1.5mm stack-height DF40 connectors.
• GTP support: High-speed GTP gigabit transceiver port capability for interfaces like PCIe 2.0.
• Artix-7 resources: Xilinx Artix-7 FPGA with substantially more resources than the Au V2.
• Stackable expansion: Stacks with Alchitry Elements to add prototyping spaces, buttons, LEDs and more.
• Independent stacks: Connectors on both sides of the board allow two independent stacks with IO not shared.
• USB connectivity: FT2232HQ supports USB -> JTAG and USB -> UART or FIFO.
• Vivado workflow: Artix 7 FPGA requires a free licence for Vivado.

Specifications:

• FPGA: XC7A100T-2FGG84I FPGA
• Logic cells: 101,440 logic cells
• DSP slices: 240 dedicated DSP48E1 slices
• Block RAM: 4,860 Kb of Block RAM Blocks
• Backside component height: no components taller than 1.5mm
• DF40 connector stack height: 1.5mm
• Board connectors: Connectors on both sides of the board allow two independent stacks (IO isn't shared)
• IO pins: 206 IO pins
• IO pair capability: All IO pairs are LVDS_25 capable inputs or TMDS_33 capable IO
• Top IO pins: 112 on the top
• Top triple voltage pins: 32 triple voltage (3.3V, 2.5V, or 1.8V) pins (16 pairs) capable of LVDS_25 IO
• Top differential pairs: 76 routed as 100 ohm differential pairs
• Top single-ended IO: Remaining IO routed as 50 ohm single ended
• Top control header IO: 8 are on the control header
• Bottom IO pins: 92 on the bottom
• Bottom differential pairs: 24 routed as 100 ohm differential pairs
• Bottom single-ended IO: Remaining IO routed as 50 ohm single ended
• Bottom control header IO: 8 are on the control header
• QWIIC connector IO: 2 on QWIIC connector
• GTP pins: 20 GTP pins broken out on the bottom
• GTP clock input pairs: 2 clock input pairs
• GTP Tx pairs: 4 Tx pairs
• GTP Rx pairs: 4 Rx pairs
• GTP bandwidth: 6.25 Gb/s bandwidth per pair
• Oscillator: 100MHz oscillator
• General purpose LEDs: 8 general purpose LEDs
• Button: 1 button (typically used as reset)
• Memory: 256MB DDR3L @ 800Mb/s (400MHz)
• Configuration flash: 32MBit Configuration FLASH
• USB interface: FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max) or FIFO (~8MB/s)
• Input voltage: 5-12V input voltage on-board power supply
• 3.3V supply: 3.3V @ 4A (IO)
• 2.5V supply: 2.5V @ 500mA (triple voltage pins, derived from 3.3V)
• 1V supply: 1V @ 4A (VCCINT)
• 1.8V supply: 1.8V @ 1.2A (VCCAUX, triple voltage pins)
• 1.35V supply: 1.35V @1.2A (DDR3L)
• 1.8V analogue supply: 1.8V @ 200mA (analog)
• 1V MGTAVCC supply: 1V @ 1.5A (MGTAVCC, derived from 3.3V)
• 1.2V MGTAVTT supply: 1.2V @1.5A (MGTAVTT, derived from 3.3V)

Ideal for advanced FPGA work where high IO count, fast transceivers and stackable expansion are needed in a compact Alchitry-format board.