Alchitry Au V2 Artix-7 FPGA Board

The Alchitry Au V2 is a powerful FPGA development board built around a Xilinx Artix 7 device. It is aimed at engineers, students and makers who are ready to move beyond microcontroller-style programming and into field-programmable gate arrays.

The board breaks out 104 IO pins across two headers and supports stackable expansion boards called "Elements", similar in idea to shields or HATs. These can add prototyping areas, buttons, LEDs and other hardware around the FPGA.

For development, the Artix 7 FPGA requires a free licence for Xilinx Vivado. The board also includes USB to JTAG and USB to UART via an FT2232HQ, plus on-board memory, oscillator, LEDs, button, QWIIC connector and power regulation.

Features:

• FPGA: XC7A35T-2FTG256I FPGA (speed and temperature grade upgrade over Au V1)
• Expansion IO: 104 IO pins broken out across two headers
• Control header: Includes IO pins for on-board LEDs, reset button, JTAG, analog/XADC connections and raw/regulated power
• QWIIC connector: QWIIC connector (shares pins on bank B)
• Clock: 100MHz oscillator
• LEDs: 8 general purpose LEDs
• Button: 1 button (typically used as reset)
• Memory: 256MB DDR3L @ 800Mb/s (400MHz)
• Configuration flash: 32MBit Configuration FLASH
• USB interface: FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max)
• Power input: 5-12V input voltage on-board power supply
• Elements expansion: Supports stackable expansion boards called "Elements" for prototyping spaces, buttons, LEDs and more

Specifications:

• FPGA: XC7A35T-2FTG256I FPGA (speed and temperature grade upgrade over Au V1)
• IO pins: 104 IO pins broken out across two headers
• Triple voltage IO pins: 22 are triple voltage (3.3V, 2.5V, or 1.8V) of which 20 are LVDS_25 capable outputs
• Differential pair routing: 44 pins are routed as 100 ohm differential pairs (includes 20 dual voltage pins)
• Remaining IO routing: Remaining IO routed as 50 ohm single ended (~90 ohm when used as diff pairs)
• Bank B 1.35V pins: 2 1.35V pins on bank B
• XADC-capable pairs: 8 pairs can be used as inputs to the XADC (0-1V input range)
• Remaining IO voltage: Remaining IO is at 3.3V
• LVDS_25 inputs: All pairs can be used as LVDS_25 inputs except three pairs on bank B
• Control header LED IO: 8 IO pins also connected to on-board LEDs
• Control header reset IO: 1 IO pin also connected to on-board reset button
• Control header JTAG: JTAG
• Control header analogue/XADC: Analog voltages and dedicated XADC input (0-1V range)
• Control header power: Raw power input/3.3V regulated output
• QWIIC connector: QWIIC connector (shares pins on bank B)
• Oscillator: 100MHz oscillator
• General purpose LEDs: 8 general purpose LEDs
• Button: 1 button (typically used as reset)
• DDR3L memory: 256MB DDR3L @ 800Mb/s (400MHz)
• Configuration flash: 32MBit Configuration FLASH
• USB bridge: FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max)
• Input voltage: 5-12V input voltage on-board power supply
• 3.3V rail: 3.3V @ 4A (IO)
• 2.5V rail: 2.5V @ 500mA (triple voltage pins, derived from 3.3V)
• 1V rail: 1V @ 4A (VCCINT)
• 1.8V rail: 1.8V @ 1.2A (VCCAUX, triple voltage pins)
• 1.35V rail: 1.35V @1.2A (DDR3L)
• 1.8V analogue rail: 1.8V @ 200mA (analog)

Documentation called out for this board includes the schematic, drawing, pinout and trace lengths, 3D Model (STEP), Simplified 3D Model (STEP), DC and AC Switching Characteristics (DS181), SelectIO Resources (UG471), Clocking Resources (UG472), and All Xilinx Artix 7 Docs.